This invention relates to a liquid crystal display and, more particularly, to a thin film transistor array incorporated therein and a process of fabrication.
A typical example of the thin film transistor array is incorporated in a liquid crystal display. The thin film transistors of the array are associated with pixel electrodes, and selectively turns on and off so as to electrically connect the data lines to the associated pixels. The thin film transistor and the associated pixel electrode form in combination a pixel.
In this application, the drain pattern and the pixel electrodes are formed on a gate insulating layer shared between the thin film transistors of the pixels. The pixels are arranged in rows, and the pixel electrodes in each row are arranged at predetermined pitches. The pixel electrodes in a row are offset from the pixel electrodes in the next row by a half of the pitch. The pixels are laid on what people call xe2x80x9cdelta patternxe2x80x9d. The array of thin film transistors laid on the delta pattern has a drain pattern, a gate pattern and a storage pattern. These patterns are in proximity to one another, and are liable to be short circuited and/or capacitively coupled to each other. Especially, when the array of thin film transistors includes the pattern formed of amorphous silicon, residual amorphous silicon is liable to be left after the patterning step. The residual amorphous silicon is causative of the short-circuit between the drain pattern and the pixel electrode and/or between the adjacent pixel electrodes. If the residual amorphous silicon is left in the gap between the delta drain pattern and the source pattern parallel to each other, the short-circuit similarly takes place therebetween. The short-circuit results in a point defect.
If the patterns such as the drain lines and the pixel electrodes are spaced from each other, the wide gap prevents the patterns from the short-circuit. However, such a wide gap forces the designer to make the pixel electrodes narrower, and, accordingly, the aperture ratio is decreased. Moreover, the small aperture ratio results in a low transmittance of the screen. Thus, the wide gap is not a good solution against the short-circuit due to the residual amorphous silicon and residual metal.
Another prior art liquid crystal display is disclosed in Japanese Patent Publication of Unexamined Application (laid-open) No. 7-199223. The prior art liquid crystal display disclosed in the Japanese Patent Publication of Unexamined Application is hereinbelow referred to as xe2x80x9cfirst prior art liquid crystal displayxe2x80x9d. FIG. 1 shows the layout of one example of the first prior art liquid crystal display. FIG. 2 shows the cross section taken along line F-Fxe2x80x2, FIG. 3 shows the cross section taken along line G-Gxe2x80x2, and FIG. 4 shows the delta pattern of thin film transistor array enclosed by broken lines H.
On a glass substrate 1 is patterned a gate layer 2, which is covered with a gate insulating layer 3 of SiNx/SiOx. An intrinsic amorphous silicon layer 4 and a heavily-doped n-type amorphous silicon layer 5 are formed on the gate insulating layer 3, and a contact slit 6 is formed in such a manner as to reach the glass substrate 1. A source pattern 7 and a drain pattern 8 are defined, and the source pattern 7 is partially overlapped with a transparent pixel electrode 9. The source pattern 7, the drain pattern 8, the transparent pixel electrode 9 and the exposed surface of the intrinsic amorphous silicon layer 4 are covered with a protective dielectric layer 10.
There remains neither residual amorphous silicon nor residual alloy in the pattern shown in FIG. 4. However, a piece of residual amorphous silicon 14 and a piece of residual alloy 15 may be left on the pattern in the fabrication process as shown in FIG. 5. The piece of residual amorphous silicon 14 and the piece of alloy 15 are causative of short-circuits. The Japanese Patent Publication of Unexamined Application teaches that the gate insulating layer 3 between the area assigned to the drain pattern 8 and the area assigned to the transparent pixel electrodes 9 is selectively etched away so as to form the contact slit 6.
FIG. 6 shows the layout of another example of the first liquid crystal display. FIG. 7 shows the cross section taken along line I-Ixe2x80x2, FIG. 8 shows another cross section taken along line J-Jxe2x80x2, and FIG. 9 shows the delta pattern of thin film transistor array enclosed in broken line K. The layers and patterns of the other example are labeled with the same references designating corresponding layers and patterns incorporated in the example of the first prior art liquid crystal display.
There is neither residual amorphous silicon nor residual alloy on the delta pattern shown in FIG. 9. However, a piece of amorphous silicon 14 and a piece of alloy 15 may be left on the delta pattern in the fabrication process as shown in FIG. 10. Even if the piece of residual amorphous silicon 14 and the piece of residual alloy 15 are left on the area between the drain pattern 8 and the transparent pixel electrodes 9 and/or the area between the adjacent transparent pixel electrodes 9, the piece of residual amorphous silicon 14 and the piece of residual alloy 15 are removed during the etching step, and the other example is prevented from the short-circuit due to the piece of residual amorphous silicon 14 and the piece of residual alloy 15.
Yet another prior art liquid crystal display is disclosed in Japanese Patent Application No. 8-525570. The prior art liquid crystal display disclosed therein is hereinbelow referred to as xe2x80x9csecond prior art liquid crystal displayxe2x80x9d. FIG. 11 shows the layout of the second prior art. FIG. 12 shows a cross section taken along line Lxe2x80x94L of FIG. 11, FIG. 13 shows another cross section taken along line Mxe2x80x94M of FIG. 11, and FIG. 14 shows the delta pattern of thin film transistor array enclosed in broken line N. The layers and patterns of the second prior art liquid crystal display are labeled with the same references designating corresponding layers and patterns of the example of the first prior art liquid crystal display. A storage pattern 12 is further incorporated in the second prior art liquid crystal display, and a slit 16 is formed in the protective dielectric layer 10. A piece of residual amorphous silicon 14 and a piece of residual transparent alloy may be left on the delta pattern as shown in FIG. 15.
The fabrication process for the second prior art liquid crystal display includes the step of forming the slit 16. Even if the piece of residual amorphous silicon 14 and the piece of residual alloy 15 are left on the area between the drain pattern 8 and the transparent pixel electrode 9 and/or the area between the adjacent transparent pixel electrodes 9, the piece of residual amorphous silicon 14 and the piece of residual alloy are etched away in the patterning step. Thus, the second prior art liquid crystal display is prevented from the short-circuit due to the piece of residual amorphous silicon 14 and/or the piece of residual alloy 15.
Following problems are encountered in the above-described prior art liquid crystal displays. The contact slit 6 is a particular feature of the delta pattern of the example of the first prior art liquid crystal display, and is formed around the pixel electrodes 9. The contact slit 6 extends between the drain pattern 8 and the pixel electrode 9, and is effective against the short-circuit therebetween due to the piece of amorphous silicon as shown in FIG. 5. However, the contact slit 6 can not prevent the drain pattern 8 and the source pattern 7 from the short-circuit. This is because of the fact that the source pattern 7 extends in parallel to the drain pattern 8 without any contact slit 6 therebetween. As to the thin film transistors arranged in the delta pattern shown in FIG. 10, the storage pattern 12 is in parallel to the gate layer 2, and is liable to be short circuited with the gate layer 2 due to the piece of residual metal 15.
The second prior art liquid crystal display is featured by the slit 16 formed in the protective dielectric layer 10. The slit 16 is also formed around the pixel electrode 9, and, accordingly, is effective against the short-circuit between the drain pattern 8 and the pixel electrode 9 as shown in FIG. 15. However, the slit 16 can not prevent the drain pattern 8 and the source pattern 7 from the short-circuit. Moreover, the slit 16 is terminated at the upper surface of the gate insulating layer 3, and can not prevent the gate layer 2 and the storage pattern 12 from the short-circuit as similar to the other example of the first prior art liquid crystal display.
Thus, both slits 6 and 16 can not perfectly prevent the conductive patterns 2/7/8/9/12 from short-circuit due to the pieces of residual conductive material 14/15.
It is therefore an important object of the present invention to provide a liquid crystal display which is free from the problems due to the pieces of residual conductive material.
It is also an important object of the present invention to provide a process for fabricating the liquid crystal display.
To accomplish the object, the present invention proposes to form contact slits between a gate pattern and a drain pattern and between a gate pattern and a storage pattern.
In accordance with one aspect of the present invention, there is provided a liquid crystal display comprising a substrate, and an array of pixels arranged in a delta pattern on the substrate and including a thin film transistor array having a gate pattern having plural gate layers formed on a major surface of the substrate, a gate insulating layer covering the gate pattern and a remaining area of the major surface, amorphous silicon layers formed on the gate insulating layers over the gate layers for providing conductive channels, a source pattern having plural source layers formed on the gate insulating layer and held in contact with the associated amorphous silicon layers, respectively, and a drain pattern having plural drain layers formed on the gate insulating layer, held in contact with the associated amorphous silicon layers, respectively, and spaced from the associated source layers and from the source layers of adjacent thin film transistors of the thin film transistor array by first regions of the gate insulating layer, respectively, plural transparent pixel electrodes formed on the gate insulating layer and connected to the source layers, respectively and storage electrode layers formed on the major surface and spaced from the gate layers by second regions of the gate insulating layer, and contact slits are form in the gate insulating layer and selectively extending through the first regions and the second regions so as to expose parts of said major surface under the second regions thereto.
In accordance with another aspect of the present invention, there is provided a process for fabricating a liquid crystal display comprising the steps of preparing a substrate having a major surface, patterning a first conductive material layer into plural gate layers and plural storage electrode layers on the major surface, covering the plural gate layers and the plural storage electrode layers with a gate insulating layer, patterning an amorphous silicon layer into plural amorphous silicon layers on the gate insulating layer, selectively etching the gate insulating layer together with a piece of residual amorphous silicon connected between two of the plural amorphous silicon layers, if any, for forming contact slits in the gate insulating layer, a piece of conductive material between one of the plural gate layers and an adjacent storage electrode layer being exposed to one of the contact slits, if any, patterning a second conductive material layer into plural drain layers and plural source layers, the piece of conductive material being split during the pattering of the second conductive material layer, patterning a transparent material layer into pixel electrodes respectively held in contact with the plural source layers, and completing the liquid crystal display.